// Example of a simple module for OpenLane flow
module counter (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       enable,
    output reg [7:0]  count
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= 8'b0;
    else if (enable)
        count <= count + 1'b1;
end

endmodule

// Chisel example: Parameterized counter
import chisel3._
import chisel3.util._

class Counter(width: Int) extends Module {
  val io = IO(new Bundle {
    val enable = Input(Bool())
    val count  = Output(UInt(width.W))
  })

  val counter = RegInit(0.U(width.W))

  when(io.enable) {
    counter := counter + 1.U
  }

  io.count := counter
}

# Amaranth example: Simple counter
from amaranth import *
from amaranth.sim import Simulator

class Counter(Elaboratable):
    def __init__(self, width):
        self.enable = Signal()
        self.count = Signal(width)

    def elaborate(self, platform):
        m = Module()

        with m.If(self.enable):
            m.d.sync += self.count.eq(self.count + 1)

        return m

# Cocotb testbench example
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge

@cocotb.test()
async def test_counter(dut):
    """Test the counter module"""
    clock = Clock(dut.clk, 10, units="ns")
    cocotb.start_soon(clock.start())

    # Reset
    dut.rst_n.value = 0
    dut.enable.value = 0
    await RisingEdge(dut.clk)
    dut.rst_n.value = 1

    # Enable counting
    dut.enable.value = 1
    for i in range(10):
        await RisingEdge(dut.clk)
        assert dut.count.value == i + 1, f"Count mismatch at cycle {i}"

// Simplified RISC-V ALU example
module riscv_alu (
    input  wire [31:0] operand_a,
    input  wire [31:0] operand_b,
    input  wire [3:0]  alu_op,
    output reg  [31:0] result
);

localparam ALU_ADD  = 4'b0000;
localparam ALU_SUB  = 4'b0001;
localparam ALU_AND  = 4'b0010;
localparam ALU_OR   = 4'b0011;
localparam ALU_XOR  = 4'b0100;
localparam ALU_SLT  = 4'b0101;
localparam ALU_SLL  = 4'b0110;
localparam ALU_SRL  = 4'b0111;

always @(*) begin
    case (alu_op)
        ALU_ADD: result = operand_a + operand_b;
        ALU_SUB: result = operand_a - operand_b;
        ALU_AND: result = operand_a & operand_b;
        ALU_OR:  result = operand_a | operand_b;
        ALU_XOR: result = operand_a ^ operand_b;
        ALU_SLT: result = ($signed(operand_a) < $signed(operand_b)) ? 32'd1 : 32'd0;
        ALU_SLL: result = operand_a << operand_b[4:0];
        ALU_SRL: result = operand_a >> operand_b[4:0];
        default: result = 32'b0;
    endcase
end

endmodule

// Formal verification properties example
module counter_formal (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       enable,
    output reg [7:0]  count
);

// Counter logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= 8'b0;
    else if (enable)
        count <= count + 1'b1;
end

`ifdef FORMAL
    // Assume reset at start
    initial assume(!rst_n);

    // Count should never exceed max value
    always @(posedge clk)
        assert(count <= 8'hFF);

    // After reset, count should be zero
    always @(posedge clk)
        if (!rst_n)
            assert(count == 8'b0);
`endif

endmodule